This invention relates to reducing leakage currents in integrated circuits.
Standby leakage current is the current which may flow through a logic circuit when a transistor within the circuit is at high impedance and attempting to hold an output voltage at a certain level. Standby leakage current can cause a loss of the signal output and can also increase power consumption of the logic circuit.
Referring to FIG. 1, an approach to reducing standby leakage current in CMOS circuits was proposed in Mutoh, et al., xe2x80x9c1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOSxe2x80x9d, IEEE Journal of Solid-State Circuits, Vol. 30, No.8, August 1995, pp. 847-854. Mutoh, et al, proposed a CMOS logic circuit 100 including a series of CMOS logic gates 102A-102B. Logic circuit 100 includes xe2x80x98sleepxe2x80x99 transistors Q1 and Q2, which are connected between the supply voltage, Vdd, and common ground, GND, respectively, to establish xe2x80x98virtualxe2x80x99 supply lines, VDDV and GNDV. The source terminals 104A-104B of the p-block transistors of each CMOS logic gate 102A-102B are connected to VDDV, while the source terminals 106A-106B of the n-block transistors are connected to GNDV. By P-block (or N-block) is meant a circuit that includes one or more p-channel (or n-channel) transistors.
In operation, in xe2x80x98sleep modexe2x80x99, SL 120 is at logic-level xe2x80x981xe2x80x99, which turns off the sleep transistors Q1 and Q2 and cuts off the leakage current that would otherwise pass through the logic gates 102A-102B. In xe2x80x98active modexe2x80x99, SL 120 is at logic-level xe2x80x980xe2x80x99, turning on Q1 and Q2, allowing the logic gates 102A-102B to evaluate. When in xe2x80x98activexe2x80x99 mode, the sleep transistors produce a VDDV which is lower than Vdd due to a voltage drop through Q1, and produce a GNDV which is higher than common ground due to a voltage drop through Q2. As a result, the effective voltage seen by the logic circuits 102A-102B is less than the difference between Vdd and common ground. This lower effective voltage increases the evaluation time of CMOS logic gates 102A-102b and therefore reduces the overall speed of the logic circuit 100.